Working at Crossbar

Crossbar Inc. is a dynamic start-up company focused on delivering solutions that will dramatically enhance the global memory storage industry. Backed by top tier investors, we have assembled an expert team of leading financial, marketing, legal and engineering professionals. We are committed to our vision of rethinking the compute/storage paradigm and ushering in a new era of artificial intelligence, IoT, machine learning and neural networks that are redefining the intersection of our physical and digital worlds, enabled by our ReRAM technology.

The following positions are currently available:

Location
  • Full time position in Santa Clara, CA
Job Description

  • Participate in Architecture and Microarchitecture specifications.
  • Verilog RTL development and debug, publish and maintain design spec and micro-architecture spec.
  • Hands on experience in all aspects of chip development process with proficiency in front end tools and methodologies.
  • Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
  • Work closely with verification team for test plan/strategy to meet all functional requirements and performance, defining verification strategy and reviewing test plan.
  • Familiarity with scripting languages like Python is a plus.
  • Familiarity with FPGA is a plus.
  • Familiarity with software and operating concepts is a plus.
  • Ability to communicate effectively across all internal groups.
  • Work closely with timing and physical team for timing closure and meet power and area goals.
Education Requirements/Preference

  • BS/MS in Electronics Engineering with minimum of 5 years of ASIC frontend & behavioral modeling experiences.
  • Strong in communication, leadership, investigation, problem solving & analytical skill.
  • Proficiency with Verilog RTL coding (LEC, CDC, DFT).
  • Well verse in interface timing budget & clock domain crossing design.
  • Familiar with SoC designs and micro-Architecture.
  • Familiar with scripting language like Python.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

In this position, you will be responsible for developing the next generation ReRAM nonvolatile memory technology and will also actively interact with process, design, product and reliability engineers for technology characterization and qualification.

Responsibilities include:

  • Electrical characterization & analysis of ReRAM non-volatile memory (NVM) devices
  • Development and optimization of NVM operation algorithms
  • Physical device modeling and simulation
  • Failure analysis of device structure and material
  • Generation of electrical design rules and assist process engineers in developing the technology design rules
  • Work closely with Process, Design, PE, Reliability, FA teams to determine intrinsic properties of the ReRAM device as well as characterization for yield, performance and reliability improvements.
Education Requirements/Preference

  • M.S. or Ph.D. in EE, Physics or related field.
  • 3-5 years of direct device engineering experience.
  • Strong in-depth understanding of solid-state physics and/or material science.
  • Experience in Restive memory ReRAM devices is highly preferred.
  • Proficiency in programming and/or script language(s) (e.g. C/C++, Python) is a plus.
  • Experience in handling large set of data and statistical analysis is a plus.
  • Excellent written and verbal communication skills.
  • Must be a hard working, self-motivated and team player.
  • Excellent written and verbal communication skills.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

As Senior Analog Design Engineer your responsibilities include:

  • Design analog circuits such as low voltage, low power bandgap, temperature sensor, charge pump, high voltage regulators, supply regulators, high speed low power opamp.
  • Simulate, optimize and document critical circuits.
  • Prepare, detailed document, and present design reviews during the design development phases.
  • Guide and work with characterization engineers to validate and characterize the design.
  • Work with yield enhancement, manufacturing, and technology development teams to debug and resolve issues related to the product design, or manufacturing yield.
  • Work with test engineering to review test flows and recommend optimum testing conditions.
  • Work with reliability engineers and assist them during qualification and failure analysis.
Education Requirements/Preference

  • MSEE with at least 8+ years of experience in design.
  • Experience with Finfet devices.
  • Experience with circuit debugging.
  • Experience with low voltage low power design techniques.
  • Experience with the design of reference circuits (voltage, current), charge pump, regulator, opamp, clock generator.
  • Experience in nonvolatile memory design is a plus.
  • Solid understanding of design/circuit and device physics.
  • Good communication and presentation skill.
  • Hands-on experience with design/simulation/verification/CAD tools.
  • Experience with silicon characterization and lab equipment.
  • Experience with supervising and mentoring other junior engineers.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

As Senior Design Engineer your responsibilities are:

  • Architect advanced memory products.
  • Design advanced nonvolatile memory circuits for memory product.
  • Design and simulate critical circuits - read path, write path.
  • Work with device engineering on optimizing the memory cell requirements given product specifications.
  • Work with product planning on optimizing the product specification.
  • Prepare, document, and present design reviews during the design development phase.
  • Work with characterization engineers to validate and characterize the design on the silicon.
  • Work with yield enhancement, manufacturing, and technology development teams to debug and resolve issues related to the product design, or manufacturing yield.
  • Work with test engineering to review test flows and recommend optimum testing conditions.
  • Work with reliability engineers and assist them during failure analysis.
Education Requirements/Preference

  • MSEE with at least 8+ years of experience in design engineering.
  • Experience with memory circuit design techniques, read/write path.
  • Experience in nonvolatile memory design is a must.
  • Experience in architecting the design for optimum performance and die size.
  • Experience in floor planning is a plus.
  • Solid understanding of design/circuit and device physics.
  • Hands-on experience with design/simulation/verification/CAD tools.
  • Good communication/presentation skill.
  • Experience with silicon characterization and lab equipment.
  • Experience with supervising and mentoring other junior engineers.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

In this position, you will be responsible for developing the next generation nonvolatile memory technology in a fast paced working environment. You will also actively interact with process and design engineers for the technology improvement.

Responsibilities include:

  • Electrical characterization & analysis of non-volatile memory (NVM) devices.
  • Development and optimization of NVM operation algorithms.
  • Physical device modeling and simulation.
  • Failure analysis.
  • Generation of electrical design rules and assist process engineers in developing the technology design rules.
Education Requirements/Preference

  • M.S. or Ph.D. in EE, Physics or related field.
  • 0-2 years of direct device engineering experience.
  • Strong in-depth understanding of solid-state physics and/or material science.
  • Experience in RRAM devices is highly preferred.
  • Proficiency in programming and/or script language(s) (e.g. C/C++, Python) is a plus.
  • Experience in handling large set of data and statistical analysis is a plus.
  • Excellent written and verbal communication skills.
  • Must be a hard working, self-motivated and team player.
Apply for Position
Location
  • Full time position in Berkeley, CA
Job Description

In this position, you will be responsible for developing semiconductor process modules and integration for the next generation nonvolatile memory technology in a fast paced working environment. You will also actively interact with device engineers for the device improvement.

Responsibilities:

  • Process development and device fabrication.
  • Responsible for two or more process modules.
  • Disciplined design of experiments.
  • Solving key process issues/challenges.
  • Thorough documentation of experiment results.
  • Meeting tight project schedules.
Education Requirements/Preference

  • M.S. or Ph.D. in Physics, Electrical Engineering, Chemical Engineering, Material Science or related field.
  • Must have 3+ years of hands-on experience with various semiconductor fabrication and characterization processes (e.g. PVD, RIE, CVD, Litho, SEM).
  • Must be a hard working, self-motivated and strong team player in a fast moving environment.
  • Experience in nonvolatile memory technology is a plus.
  • Strong ability to handle multiple tasks.
  • Flexibility to tune work schedule for projects.
  • May require to work during alternative business hours and weekends.
Apply for Position
Location
  • Full time position in Santa Barbara, CA
Job Description

In this position, you will be responsible for developing semiconductor process modules and integration for the next generation nonvolatile memory technology in a fast paced working environment. You will also actively interact with device engineers for the device improvement.

Responsibilities:

  • Process development and device fabrication.
  • Responsible for two or more process modules.
  • Disciplined design of experiments.
  • Solving key process issues/challenges.
  • Thorough documentation of experiment results.
  • Meeting tight project schedules.
Education Requirements/Preference

  • M.S. or Ph.D. in Physics, Electrical Engineering, Chemical Engineering, Material Science or related field.
  • Must have 3+ years of hands-on experience with various semiconductor fabrication and characterization processes (e.g. PVD, RIE, CVD, Litho, SEM).
  • Must be a hard working, self-motivated and strong team player in a fast moving environment.
  • Experience in nonvolatile memory technology is a plus.
  • Strong ability to handle multiple tasks.
  • Flexibility to tune work schedule for projects.
  • May require to work during alternative business hours and weekends.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

As a Technical Marketing at Crossbar, Inc., your responsibilities include, but are not limited to the following:

Technical Spec writer:

  • Translate marketing and customer requirements into architecture definition, performance requirements, component level and block level definition and specifications.
  • Work with Crossbar design, validation and device teams to ensure successful implementation and demonstration of new storage and memory solutions.
  • Produce technical product brief, applications notes, whitepapers and technical datasheets.

Marketing: Value positioning

  • Analyze market segments and trends (data centers, mobile, industrial / automotive / medical, consumer electronics, IoT, artificial intelligence).
  • Analyze memory market and competitive positioning vs other memory technologies (Flash, DRAM, SRAM, ReRAM, MRAM, PCM).

PR: Internal and external communications

  • Production of internal reports, customer presentations, white papers, articles and application notes.
  • Drive Marketing Communication and PR team activities.
  • Drive exhibition booth setup and related activities.
  • Production of website collateral: infographics, block diagrams, video scripts.
Education Requirements/Preference

  • This position requires a BSEE/MSEE or related engineering major with minimum of 5 years of marketing experience in Semiconductor industry or IP licensing.
  • Experience on Technical Marketing across several market segments: data centers, mobile, industrial / automotive / medical, consumer electronics, IoT, artificial intelligence.
  • Understanding on semiconductor industry, system architectures and memory market is highly desirable.
  • The candidate should demonstrate ability to comprehend and consider both technical and marketing information and possess excellent communication, presentation and interpersonal skills.
  • Excellent graphic design skills, expert in powerpoint.
  • High-energy, self-motivated, self-directed, must have demonstrated ability to influence.
  • The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
Apply for Position
Location
  • Full time position in Santa Clara, CA
Job Description

In this position, you will be responsible for testing non-volatile memory (NVM) devices and advanced CMOS logics in a fast paced working environment.

  • Electrical characterization of non-volatile memory (NVM) devices and advanced CMOS logics.
  • Data extraction and report generation.
  • Development and optimization of NVM operation algorithms.
Education Requirements/Preference

  • M.S. in EE, Physics or related field.
  • 1-3+ years of direct device and test engineering experience.
  • Proficiency in programming and/or script language(s) (e.g. C/C++, Python).
  • Memory testing experience is a plus.
  • Experience in handling large set of data and statistical analysis.
  • Excellent written and verbal communication skills.
  • Must be a hardworking, self-motivated and team player.
Apply for Position

To apply, please email or mail us your letter of application, a resume and the name, mailing address, email address, and telephone number of three professional references, one of which must be a current supervisor. Additionally, please indicate in your cover letter where you first learned of this position.