Breakthrough Semiconductor ReRAM Technology

CrossBar is advancing the frontier of memory and silicon systems, building architectures that combine performance, security, and verifiability at the hardware level.
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ReRAM

Purpose-built memory and silicon architectures engineered for performance, security, and hardware-level verifiability.

Hardware Wallets

Open-source from chip RTL to application layer. IRIS-inspectable silicon, verifiable firmware. No closed components.

MPC

Seedless key management on a secure element. 10x faster than cloud-based MPC. Local threshold signing with no cloud dependency.

// By the Numbers

Why ReRAM is Fundamental

Traditional flash memory was designed for data storage, not for safeguarding cryptographic secrets. ReRAM changes the physics of what is possible.
200+

Patents Worldwide

22nm

ReRAM Process Node

150yr

Data Retention

100%

Open Source

ReRAM Highlights

High Density
Terabyte-scale on-chip storage with minimal layout overhead. Ultra-dense, stackable 3D cross-point arrays.
Energy Efficient
5× less energy than eFlash, 20× less than NAND, 30× less than SPI Flash, and 40× less than BLE.
High Performance
20ns read, 12μs write, no erase latency. 100× faster reads, and 1,000× faster writes than traditional memory.
Enhanced Security
Tamper-resistant storage for cryptographic keys. Prevents extraction and supports secure keys.
Read ReRAM Paper

World's First Secure Processing Unit (SPU)

Innovative products leveraging CrossBar architecture for secure computing.
// FLAGSHIP SECURITY CHIP

Daric SPU

DARIC is CrossBar’s purpose-built secure processing unit, combining compute, cryptographic acceleration, and ReRAM-based memory into a single monolithic architecture. Designed from the ground up for security and performance, it eliminates the need for fragmented systems and exposed interconnects.

Built on advanced-node ReRAM, DARIC enables physically secure key storage, high-speed execution, and long-term data integrity within one unified chip.

  • Integrated ReRAM for secure, high-retention memory
  • On-chip cryptographic engine (ECDSA, SHA, PQC-ready)
  • Monolithic design reduces attack surface
  • Open architecture for verifiability and auditability
Read the Whitepaper GitHub Chip Design
// MPC POWERED PRODUCT

Sovrency Wallet

Multi-Party Computation moves key management from a single secret to a distributed protocol. CrossBar's E-MPC is the first implementation that runs entirely on a secure element — no cloud required.

  • No seed phrase or single point of compromise
  • Local, device-based MPC signing
  • Flexible threshold configuration (T-of-N)
  • Built on DARIC secure processing architecture
Watch MPC Demo
// OPEN SOURCE HARDWARE

“If you can’t verify it, you don’t own it.”

Every layer verifiable. Every line auditable. From silicon to firmware — CrossBar is building the hardware foundation the open-source community has been waiting for.

SW SDK Source
Board-Level Hardware Source
Leadership

Meet the Team

Mark Davis, CEO

Serial entrepreneur with strong system expertise. Previously held executive roles at Intel, VIA, and LSI Logic.

Sung Hyun Jo, CTO

Founder of CrossBar and top expert in cryptography and AI. Currently holds over 200+ patents.

Elaine Wang, CBO

Cofounder & CEO of Metropolis, launching sovereign-backed digital residency programs. Organizer of Palau Blockchain Summit and founding advisor of AAG Ventures.

Get in touch with our team

Connect with CrossBar

CrossBar is advancing the frontier of modern computing through memory and silicon innovation. We design high-performance, secure, and verifiable hardware systems that push beyond traditional architectures. We collaborate with engineers, researchers, and builders working at the edge of hardware, systems, and applied technologies.

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