CrossBar and the World’s True Open Source Hardware for Crypto Wallet: A New Era for Crypto Security
CrossBar’s Open-Source Security Processing Unit Is Bringing Silicon Transparency to the Crypto Industry for the First Time
The CrossBar Team
5/13/20265 min read
We’re excited to share CrossBar’s latest milestone in open-source hardware security. In this article, we explore what truly open silicon means for the crypto industry — and why it matters now.
1. The Architecture Behind the Breakthrough
For decades, the security hardware industry has operated on a foundational contradiction: trust us. Companies producing secure elements, hardware wallets, and cryptographic chips ask users to place enormous faith in silicon they cannot inspect, verify, or scrutinize. That black-box model is beginning to change — and CrossBar is helping lead that shift.
CrossBar’s Security Processing Unit (SPU), developed alongside some of the world’s most respected open-source hardware advocates, represents a major step toward commercially viable, truly open hardware security. With open Register-transfer Level (RTL) code, publicly accessible hardware specifications, and an expanding open-source software ecosystem, CrossBar is pushing the crypto industry closer to a future where users can finally verify the hardware securing their assets. For the crypto community, where the phrase “don’t trust, verify” is a core principle, this development is nothing short of transformational.
CrossBar’s open-source hardware journey took a decisive turn through its collaboration with the Baochip-1x project and open-source security advocate Bunnie Huang. CrossBar’s engineering team had been evaluating a choice between a RISC-V architecture and an ARM Cortex-M7 core — and the calculation that followed was elegant in its simplicity. Including both cores would add only a few cents to the die cost, so CrossBar opted for both. Bunnie Huang contributed a fully open-source RISC-V core to the effort, and the chip proceeded to tape-out. The result is the CrossBar Daric SPU, a 22nm system-on-chip whose RTL is publicly available on GitHub for independent verification, constrained only by applicable third-party licensing requirements. Baochip-1x is one of the first partner applications built on top of the Daric platform.
This matters because RTL is the blueprint of a chip: the human-readable description of how every logic gate is wired together. Publishing RTL is the hardware equivalent of releasing source code. It means researchers, security auditors, and developers around the world can examine exactly what the chip does, confirm that no hidden backdoors exist, and build confidence from the ground up.
2. IRIS Inspection: Seeing Inside the Silicon
Beyond the RTL release, the Baochip-1x — an application built on the Daric platform — became the proving ground for one of the most important emerging technologies in open-source hardware: IRIS inspection. IRIS (Infrared In-Situ inspection) is a non-destructive technique for visually examining the internal structure of a fabricated chip without decapping or destroying it. CrossBar’s Daric SPU served as the test vehicle for advancing this foundational technology, and several of the high-resolution 22nm IRIS images now circulating within the hardware security community were captured directly from Daric silicon validated through the Baochip-1x program.
The implications for the crypto space are significant. Hardware wallets and secure elements have long been treated as “trust anchors” — devices users rely on to protect private keys. But that trust has historically been unverifiable. IRIS inspection, combined with open RTL, begins to close that gap. For the first time, a security chip can be physically inspected to confirm that what was manufactured matches what was designed. The “don’t trust, verify” ethos can now be applied at the silicon layer.
3. Why This Matters for Crypto: The Community Chip Model
Vitalik Buterin, the founder of Ethereum, has spoken directly about why open-source silicon is an absolute necessity for the crypto ecosystem. In a talk at Ethereum Singapore, he made the case that the integrity of the entire decentralized finance stack depends on hardware that can be independently audited — hardware that users don’t simply have to trust.
CrossBar’s approach aligns with this vision, and the economics reinforce it. As semiconductor manufacturing advances, chip design costs continue to rise dramatically, while the marginal cost per gate falls at scale. This creates a powerful incentive for multiple parties to share a single tape-out that serves each participant’s needs: a “community chip.”
CrossBar envisions these community chips addressing different operational regimes. An NFC-powered regime targets ultra-low power applications running at 3–10 milliwatts, using high-threshold voltage transistors and subthreshold logic on larger process nodes. A client-side regime serves battery-powered devices like hardware wallets and secure mobile accessories. A network-side regime addresses infrastructure with fewer power constraints. Each regime has distinct requirements, and an open hardware platform allows the community to adapt designs accordingly rather than being locked into a vendor’s proprietary choices.
4. Open Source by Design: The GitHub Ecosystem
5. Two Fronts, One Goal
Achieving truly open, production-worthy silicon requires attacking the problem from two fronts.
Front A starts from open design flows and works to make them production-worthy. It democratizes prototyping and lowers barriers to entry, but today’s open flows still can’t reliably produce the high-volume, competitive chips that end up in real devices.
Front B takes the opposite approach: start from proven, production-grade design flows and work systematically toward openness, prioritizing security-critical IP for public release while accepting “open market” availability for generic components. This is CrossBar’s lane — the CrossBar SPU was built on a 22nm commercial process with full production rigor, then its security-critical RTL was opened under CERN-OHL-W for public audit.
The two fronts are complementary, not competing. Each delivers independent value to different communities, and there’s no reason to work on them sequentially. The SPU chip is the clearest proof yet that production-worthy and genuinely open are not mutually exclusive.
CrossBar has indicated that community engagement will continue to expand. Better documentation for configuring the open card is in progress, alongside deeper documentation for the Data Access Control function. The developer kit program is being built out to allow anyone — individual hackers, startups, established hardware companies — to develop products on top of CrossBar’s open foundation.
For the crypto industry, this trajectory points toward a future where hardware wallets, key management devices, and secure signing modules can be audited from the gate level up. The silicon layer — long the final, opaque frontier in the security stack — is becoming as transparent as the open-source software running above it.
CrossBar’s work is a reminder that “open source” is not just a licensing choice. It is a philosophy, a trust model, and increasingly, a technical necessity for any infrastructure that claims to be trustworthy. In crypto, where trust is the product, that is a very big deal indeed.
— The CrossBar Team
CrossBar’s commitment to openness extends beyond silicon design.
The company has structured its broader ecosystem around open-source access and community development. Core hardware components are released under the CERN-OHL-W license, a copyleft license specifically designed for open hardware that requires derivative works to remain open as well.
A ThreadX-based system with complete drivers for the PHSM8 is already live. An ARM software package has also been released open-source, with additional tooling on the way.
Released GitHub repositories include:
CrossBar Daric SDK: SDK for developing firmware on SPU embedded platforms
CrossBar Daric Hardware: Chip specification and reference design
The goal is to give developers a flexible, crypto-native hardware platform for building everything from hardware wallets to authentication devices and secure signing infrastructure.