Crossbar – A Completely New Class of RRAM

Crossbar RRAM. Three layers: top electrode, switching medium with ions and bottom electrode

Crossbar RRAM technology is based on three simple layers:

  • Non-metallic bottom electrode
  • Amorphous silicon switching medium
  • Metallic top electrode

The resistance switching mechanism is based on the formation of a filament in the switching material when a voltage is applied between the two electrodes. This simple and very scalable memory cell structure enables an entirely new class of RRAM, which can be easily incorporated into the back-end-of-line of any standard CMOS manufacturing fab.

Crossbar has successfully developed its demonstration product in a commercial fab. This working silicon is a fully integrated monolithic CMOS controller and memory array chip.

About Crossbar RRAM Technology

With its multiple bits per cell and 3D stacking capability, Crossbar has significant density advantages over traditional memory solutions.

  • Low temperature cell: enables the integration of multiple memory array layers on top of the CMOS controller and provides potential 1TB storage capacity.
  • Provides 1/10th of programming current for low-power applications, 2 to 4 times more data (MLC) and 1 to 3 more stacking layers for greater density.
  • Cell switching based on field dependent switching: leads to no read- or program-disturb below the critical field.
  • No joule heating: eliminates cross talk between the cells during the switching event and allows for larger arrays and higher density.
  • No need for high voltage devices for multiple program/erase cycles: allows smaller die sizes and cheaper process technology.
  • Mitigated potential memory loss from the program-state and the erase-state due to our field dependent switching phenomena.
  • Large on/off ratio: improves as cell size shrinks.
  • Tight distribution across the wafer: provides good margin for product design.
  • No diffusion of metal during normal backend thermal processing: enables easily port to backend CMOS processing.