CrossBar's Story and Vision

We’re excited to share a message from our CEO, Mark Davis. In this article, he shares CrossBar’s vision, our core technologies, and the thinking behind our work in secure, open-source hardware.

Since CrossBar is becoming more public-facing, I wanted to take this opportunity to introduce our company, our technology, and our vision.

At first glance, the company might appear to be in several disconnected areas, but they are in fact all closely related.

CrossBar, Inc. was founded in 2010 with technology from the University of Michigan, backed by Kleiner Perkins. Early days were spent developing IP in the area of Resistive Random Access Memory (ReRAM). The purpose of ReRAM is that it is a Non-Volatile Memory (NVM) technology that can be fabricated in a logic process — similar to embedded floating-gate flash, but more amenable to porting into smaller process geometries. In contrast, embedded floating-gate flash is typically found in 40–130nm chips.

CrossBar developed many ReRAM innovations, which were ultimately licensed to licensees with manufacturing capabilities. CrossBar then shifted to developing products around ReRAM.

There are several independent reasons for putting NVM on the same die as logic, and so ReRAM appears in various unrelated product areas. CrossBar has mostly focused on security products, where raw private key material must be stored privately but made available to logic (such as signature calculation logic). Also, among NVM technologies, ReRAM is especially robust and inspection-resistant.

ReRAM

SPU

As CrossBar looked into existing logic chips with NVM, we realized that incumbents bifurcated their product lines into two segments with quite opposite requirements:

• Microcontroller (MCU), which does not have the overhead of physical security but is very flexible and powerful.

• Secure Element (SE) chips, which do have physical countermeasures. SEs are directed primarily at very cost-sensitive commodity markets (bank cards, SIM cards), where it doesn’t make sense to carry the overhead of flexibility. They are also slow-moving in terms of product introductions due to burdensome certification requirements.

Meanwhile, it seemed like the mathematical field of cryptography was exploding with innovation. But how do you create innovative security products based on this innovation if the flexible chips aren’t secure and the secure chips aren’t flexible? This led us to the idea of combining the physical security of an SE with the flexibility and memory size of an MCU, which we called a Secure Processing Unit (SPU). Our first chip, the “CrossBar SPU,” is a first take on this concept.

An SPU could be used in many fields (IoT, transportation, medical, infrastructure, etc.). But we found immediate engagement in the blockchain field, and that has consumed most of our attention so far.

Hardware

One lesson from our previous experiences in semiconductors is that it is difficult to sell a chip by itself. It is really software and applications that sell chips. So we simultaneously began developing boards and reference applications around the chip, such as the PHSM 8 and PHSM 6. These are designed with blockchain in mind but could also be used in other fields (for example, the PHSM 8 is FIDO2 certified).

In addition to the hardware, we wanted to exploit the advantages of an SPU by developing specific application software. In other words, having high processing power under an umbrella of countermeasures seems useful — but for what specifically? Two examples we developed are Post-Quantum Cryptography (PQC) and Multi-Party Computation (MPC).

Although CrossBar SPU was designed without PQC-specific accelerators, it ends up doing a decent job of PQC simply by virtue of having high compute capability (figures to be published soon in another article).

We also developed a full MPC wallet. MPC is an ideal arrangement for preventing key loss since it avoids any single point of failure. However, the compute load is too heavy for a typical Secure Element. So our SPU is an ideal enabler for fast, secure, private client-side signing. As far as we know, ours is the first MPC wallet in the world with a hardware wallet signer.

We developed several optimizations on existing MPC protocols to make the entire system very fast. You can see a demonstration of the system in this video.

Applications, PQC, MPC

Another facet of CrossBar SPU came through our engagement with Bunnie Huang and Baochip 1x. Bunnie is a world-renowned hacker and open-source security advocate. He suggested a RISC-V core with an MMU would provide something unique. He elaborates on it in this article.

We were originally debating between using RISC-V or an ARM M7, but we quickly calculated that just including both cores would only cost a couple of pennies in die size. So Bunnie contributed a fully open-source RISC-V core, and we taped out the chip. Bunnie was instrumental in leading us to open-source the RTL for the chip (to the extent allowable by third-party constraints).

He also used the chip to further develop his “IRIS inspection,” a foundational technology for open-source silicon. The 22nm images in this article are CrossBar SPU / Baochip 1x.

It turns out this uniqueness of the SPU, especially an open-source SPU, has gathered a lot of attention. So, in order to enable community engagement, we decided to open-source our hardware and software drivers, making them generally available for developers. We are still adding to this, but as of this writing, a ThreadX-based system with complete drivers for the PHSM8 is live on our GitHub.

We will be rolling out various engagement methods, including the ability for anyone to develop with several open-source hardware form factors or even base a customer-branded end-user product on our hardware.

Open Source

Community Chip

Meanwhile, a growing set of other entities and individuals are recognizing the need for open-source silicon and hardware. For example, Vitalik Buterin, founder and creator of Ethereum, spoke very directly on the absolute necessity for open-source silicon from Ethereum Singapore (starting at 3:05 in this video).

The economics of chips, especially as geometry advances, is that non-recurring costs become high, but gates become very cheap. This suggests that multiple interested parties have strong motivation to share a tapeout that serves each party’s needs — a so-called “community chip.”

CrossBar SPU is already an example of a small “community chip,” since the same tapeout is both the CrossBar SPU and the BaoChip 1x.

We have been in energetic discussions with more parties about a successor to the SPU, incorporating many more features. Some press releases on this topic will come soon.

In summary, we find that several fundamental technologies we have developed are converging synergistically. ReRAM naturally supports advanced-node security products, the SPU concept enables innovation, and open-source development is a natural fit with the ethos of blockchain systems. For these reasons, we find increasing interest in our unique hardware and software from a wide set of developers and users.

So we invite you to follow our story or become a part of it through our developer community.

Mark Davis

CEO of CrossBar, Inc.

Summary

CrossBar Inc.

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